Each flash memory cell in a NAND architecture features a transistor with a control gate and a floating gate. To store information, a charge level is written to the cell by adding a specified amount of charge to the floating gate through Fowler-Nordheim tunneling by applying a relatively large voltage to the control gate (see: R. Bez, E. Camerlenghi, A. Modelli, and A. Visconti. “Introduction to
Flash Memory,” Proc. IEEE, 91(4), April 2003). On a multi-level cell (MLC) flash memory the target charge level may have several values (for example 4 charge levels for a 2-bits per cell memory).
FIG. 1 illustrates a prior art flash memory cell 10 that is a part of a NAND flash memory. The flash memory cell 10 includes a transistor 10′ and various lines that connect the transistor 10′ to other elements of the flash memory.
The transistor 10′ includes a control gate 23, a floating gate 21, a bulk (that includes a P-well 16 and two N+ regions 15 that define a substrate 16′, a source 14 and a drain 13), and two oxide layers 22 and 20 that are placed between the control gate 23, the floating gate 21 and the bulk.
The control gate 21 is connected (via contact 24) to a wordline to receive wordline voltage 25, the drain 13 is connected to a sense amplifier comparator 12 that outputs a bit line signal over bit line 11. The source 14 is illustrates as being connected to a capacitance 19 that is grounded.
In order to read the flash memory cell, the charge level written to the floating gate 21 is detected by applying a specified word-line voltage 25 to the control gate 23 and measuring transistor drain current that flows through drain 13.
The drain current is compared to a current threshold by the sense amplifier comparator 12.
If the drain current is above the current threshold, then the word-line voltage 25 was sufficient to turn on the transistor 10′, indicating that the charge written to the floating gate 21 was insufficient to prevent the transistor 10′ from turning on. If the drain current is below the threshold, the charge added to the floating gate 21 was sufficient to prevent the applied word-line voltage 25 from turning on the transistor 10′.
The sense amplifier comparator 12 provides one bit of information about the charge level present in the floating gate 21. A bit error occurring at this threshold-comparison stage is called a raw bit error. Analog impairments of the sense amplifier comparator 12 and the threshold voltage read circuitry (not shown) introduce noise in addition to the variable charge level of the floating gate 21.
Once the reading attempt the inaccuracy of the measurement of the charge level can not be compensated in analog manners.
The word-line voltage 25 (threshold voltage) required to turn on a particular transistor can vary from cell to cell for a variety of reasons. For example, the floating gate can be overcharged during the write operation, the floating gate can lose charge due to leakage in the retention period, or the floating gate can receive extra charge when nearby cells are written.
When flash memory cells are read with multiple read thresholds then the read threshold that causes the read result of the flash memory cell to change (in comparison to the read results obtained using lower read thresholds) can be referred to a change-inducing read threshold. The change-inducing read threshold may equal the threshold voltage required to turn on a particular transistor but may be higher then that threshold voltage.
A dominant effect, in floating gate NAND Flash technology, for change over time is known as detrapping, where there is charge leakage from the floating gate. Detrapping increases threshold voltage variance with the program erase (P/E) cycles. As the number of P/E cycles increases, the number of traps also increases.
FIG. 2 demonstrates a prior art threshold voltage distribution and various read thresholds. A single read threshold is applied per each read attempt.
The threshold voltage distribution 200 of a 2 bit per cell (bpc) flash memory page (physical page) includes four lobes—201-204. The physical page can be used for storing a Most Significant Bit (MSB) logical page and a Least Significant Bit (LSB) logical page. The MSB page can be read by a single read attempt that uses MSB read threshold Xth,1 212, where cells which correspond to threshold voltage higher than Xth,1 212 are assigned a logical ‘0’ and all other cells are assigned a logical ‘1’. The LSB page can be read by using two read threshold Xth,0 211 and Xth,2 213, where all the cells which are located between these thresholds are assigned a logical ‘0’ value, and other cells are assigned a ‘1’.
Since the statistical distribution of the threshold voltage changes over the Flash device life span, a read operation may require learning the statistics and only then placing the thresholds for the read operation which is used as input for the decoder. In case there are not too many errors, a hard input, obtained from a single read attempt, for the decoder may suffice once the statistics is known up to a sufficiently high accuracy. It is mainly required for setting read threshold such that a minimal number of read errors is obtained for the decoder inputs.
When there are relatively many errors, it may not be enough to provide just a single hard decision input, which is obtained by a single read, to the decoder.
In such cases, a soft decoder may be applied when soft information, or reliability information, for each bit (a read result of a single read attempt of a single flash memory cell) is provided to the decoder. This information is achieved by performing multiple read operations using different read thresholds.
In FIG. 2, for example, reading the MSB page bits with soft input may require sampling multiple times around threshold Xth,1 and to provide reliability metrics accordingly. For providing soft input to the decoder when reading the LSB page bits, it is required to perform multiple read operations around Xth,0, and Xth,2. For fast—and joint sampling of Xth,0, and Xth,2 it may be suggested to sample once around Xth,1 and then perform multiple samples around Xth,0, and Xth,2 obtained by LSB page type reads (which saves twice the number of read operations).
For soft decoding, reliability metrics called soft information per bit are required. This is obtained by performing multiple reads from the Flash, where each read operation uses different read thresholds. The read thresholds must be configured such that soft metrics, called log-likelihood ratio (LLR), or any approximation, can be computed per bit.
The definition of an LLR is
      LLR    ⁡          (              b        i            )        =      log    ⁡          (                        P          ⁡                      (                                          b                i                            =                              1                |                y                                      )                                    P          ⁡                      (                                          b                i                            =                                                -                  1                                |                y                                      )                              )      where y is the channel output and bi is the ith bit of some page (which is a read result of a certain flash memory cell of a physical or logical page, the read result is obtained when using a certain read threshold), and the values of bi can be ‘−1’ or ‘1’.
Flash memory cells can be read by performing a high resolution read operation. The high resolution read operation typically includes multiple read attempts that involve using read thresholds that are proximate to each other. Read results and soft information are provided to an error correction decoder.
The read results can be of relatively low reliability. There is a growing need to increase the reliability of read results of flash memory cells.